Image from page 17 of “randomCorporation :: PFCLGY024-04 Colleague and Colleague Plus Users Guide Aug1988” (1919)

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Image from page 17 of “randomCorporation :: PFCLGY024-04 Colleague and Colleague Plus Users Guide Aug1988” (1919)
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Identifier: bitsavers_randomCorpolleagueandColleaguePlusUsersGuideAug198_16743724
Title: randomCorporation :: PFCLGY024-04 Colleague and Colleague Plus Users Guide Aug1988
Year: 1919 (1910s)
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Subjects: key colleague host menu function modem cursor esc select terminal programmable function telephone number host system control sequences return key internal modem default settings random corporation function key edit key
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2-7 –

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^ > Direct Connection to Host Computer (RS-232) 2-8 o r- Getting Started r*—

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Image from page 26 of “calcomp :: H-84-0045B vistagraphic DR11W DR11B DR11C and DR11B parallel interface users manual Nov1984” (1919)
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Identifier: bitsavers_calcompH8411WDR11BDR11CandDR11Bparallelinterfaceus_25203025
Title: calcomp :: H-84-0045B vistagraphic DR11W DR11B DR11C and DR11B parallel interface users manual Nov1984
Year: 1919 (1910s)
Authors:
Subjects: interface host dma parallel vistagraphic input cables spi assy parallel interface circuit card parts list word count register bit host interface zone ltr memory address interconnect panel inches tolerances
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1089623 1089756 Connection Diagram DR11««C (VIOOO, V3000)with Interconnect Panel 5802528G2CIRCUIT CARD

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5977207 H-84-0045-027 Connection Diagram DRl1-C (VIOOO, V3000)without Interconnect Panel 18 SECTION 3INTERFACE SIGNALS NOTE All references to input and output in thisdocument are with respect to SelectableParallel Interface (SPI) . Input means inputfrom the Vistagraphic system to the hostcomputer; output means output from thehost computer to the Vistagraphic system. 3c1 INPUT TRANSFER SIGNALS (SPI to HOST) MNEMONIC NAME FUNCTION IDOO IN-ID 15 IN Input Data Levels presented on theselines are read directly tomemory when the host interfaceperforms a DATO bus cycle.Data must remain stable forthe entire DATO bus cycle. CI CTRL CI Control This control signal specifiesthe type of bus cycle the hostinterface will perform.(Logic 0 = output, logic 1 =input.) REQA Cycle Request A Generated by the 24 bit SPI,REQA signals the hostinterface to initiate atransfer, and sets the cycleflip-flop in the host. CYCLEinitiates the sequence ofrequesting bus use (DEC HOST)and triggers the bus cycleafter the h

Note About Images
Please note that these images are extracted from scanned page images that may have been digitally enhanced for readability – coloration and appearance of these illustrations may not perfectly resemble the original work.